1. Field of the Invention
This invention relates to a package for semiconductors, and more particularly to a fan out type wafer level package.
2. Description of the Prior Art
The semiconductor technologies are developing very fast, and especially semiconductor dies have a tendency toward miniaturization. However, the requirements for the functions of the semiconductor dies have an opposite tendency to variety. Namely, the semiconductor dies must have more I/O pads into a smaller area, so the density of the pins is raised quickly. It causes the packaging for the semiconductor dies to become more difficult and decrease the yield.
The main purpose of the package structure is to protect the dies from outside damages. Furthermore, the heat generated by the dies must be diffused efficiently through the package structure to ensure the operation the dies.
The earlier lead frame package technology is already not suitable for the advanced semiconductor dies due to the density of the pins thereof is too high. Hence, a new package technology of BGA (Ball Grid Array) has been developed to satisfy the packaging requirement for the advanced semiconductor dies. The BGA package has an advantage of that the spherical pins has a shorter pitch than that of the lead frame package and the pins is hard to damage and deform. In addition, the shorter signal transmitting distance benefits to raise the operating frequency to conform to the requirement of faster efficiency. For example, the U.S. Pat. No. 5,629,835 discloses a BGA package, by Mahulikar et al; the U.S. Pat. No. 5,239,193 discloses another package that the FR4 substrates having a pattern of conductive traces thereon are mounted on a PCB; the Taiwan patent No. 177,766 discloses a fan out type WLP, by the inventor of the present invention.
Most of the package technologies divide dies on a wafer into respective dies and then to package and test the die respectively. Another package technology, called “Wafer Level Package (WLP)”, can package the dies on a wafer before dividing the dies into respective dies. The WLP technology has some advantages, such as a shorter producing cycle time, lower cost, and no need to under-fill or molding. The U.S. Pat. No. 5,323,051, “Semiconductor wafer level package”, is disclosed a WLP technology by Adams et al. The technology is described as follow. As shown in FIG. 1, a die 4 is formed on a surface of a semiconductor wafer 2, and a cap wafer 6. with a predetermined pattern of frit glass walls 8 as a bonding agent is deposited on a surface of the semiconductor wafer 2, such that the die 4 is completely surrounded by the frit glass walls 8. Then, a surface of the semiconductor wafer 2 without the die 4 is polished to reduce the height of the semiconductor wafer 2; the process is generally called “Back Grinding”. The die 4 is hermetically sealed in a cavity of predetermined dimensions formed by a combination of the semiconductor wafer 2, the cap wafer 6, and the frit glass walls 8. A plurality of metal traces 10 forms a plurality of electrodes on semiconductor substrate wafer 2 which provide electrical coupling to die 4. A plurality of wires 12 is bonded to a plurality of pads formed on exterior portions of metal traces 10, and extends through hole 14 and is coupled to external electrical dies (not shown).
As aforementioned, the size of the die is very small, and the I/O pads are formed on a surface of a die in the conventional arts. Therefore, number of the pads is limited and a too short pitch among pads results in a problem of signal coupling or signal interface. The solder is also to form a solder bridge easily due to the too short pitch among pads. Moreover, the size of die gradually become smaller and the packaged IC of the die does not have standard size by some package technologies (such as chip size package), but test equipment, package equipment, etc. for some fixed sizes die or packages can not be kept on using